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? 2003-2012 microchip technology inc. ds21117b-page 1 mcp6s21/2/6/8 features ? multiplexed inputs: 1, 2, 6 or 8 channels ? 8 gain selections: - +1, +2, +4, +5, +8, +10, +16 or +32 v/v ? serial peripheral interface (spi) ? rail-to-rail input and output ? low gain error: 1% (max) ? low offset: 275 v (max) ? high bandwidth: 2 to 12 mhz (typ) ? low noise: 10 nv/ ? hz @ 10 khz (typ) ? low supply current: 1.0 ma (typ) ? single supply: 2.5v to 5.5v typical applications ? a/d converter driver ? multiplexed analog applications ? data acquisition ? industrial instrumentation ? test equipment ? medical instrumentation package types description the microchip technology inc. mcp6s21/2/6/8 are analog programmable gain amplifiers (pga). they can be configured for gains from +1 v/v to +32 v/v and the input multiplexer can select one of up to eight chan- nels through an spi port. the serial interface can also put the pga into shutdown to conserve power. these pgas are optimized for high speed, low offset voltage and single-supply operation with rail-to-rail input and output capability. these specifications support single supply applications needing flexible performance or multiple inputs. the one channel mcp6s21 and the two channel mcp6s22 are available in 8-pin pdip, soic and msop packages. the six channel mcp6s26 is avail- able in 14-pin pdip, soic and tssop packages. the eight channel mcp6s28 is available in 16-pin pdip and soic packages. all parts are fully specified from -40c to +85c. block diagram v ref ch0 v ss si sck 1 2 3 4 8 7 6 5 v dd cs v out ch1 ch0 ch2 cs si 1 2 3 4 14 13 12 11 v ref v ss v out 5 6 7 10 9 8 ch3 sck v dd ch5 ch4 ch0 v out ch1 v ss cs 1 2 3 4 16 15 14 13 si sck 5 6 7 12 11 10 ch2 ch4 ch7 v dd ch5 8 9 so ch6 ch3 so ch1 ch0 v ss si sck 1 2 3 4 8 7 6 5 v dd cs v out mcp6s21 pdip, soic, msop mcp6s26 pdip, soic, tssop mcp6s28 pdip, soic mcp6s22 pdip, soic, msop v ref v out v ref v dd cs si so sck ch1 ch0 ch3 ch2 ch5 ch4 ch7 ch6 v ss 8 r f r g mux spi? logic por gain switches + - resistor ladder (r lad ) single-ended, rail-to-rail i/o, low gain pga
mcp6s21/2/6/8 ds21117b-page 2 ? 2003-2012 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd - v ss .........................................................................7.0v all inputs and outputs ....................... v ss - 0.3v to v dd +0.3v difference input voltage ........................................ |v dd - v ss | output short circuit current...................................continuous current at input pin ?????????????????????????????????????????????????????????????? 2ma current at output and supply pins ???????????????????????????????? ? 30 ma storage temperature .....................................-65c to +150c junction temperature .................................................. +150c esd protection on all pins (hbm;mm) ?????????????????? ?? 2 kv; 200v ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specific ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. pin function table name function v out analog output ch0-ch7 analog inputs v ss negative power supply v dd positive power supply sck spi clock input si spi serial data input so spi serial data output cs spi chip select v ref external reference pin dc characteristics electrical specifications: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref = v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 to ch7 = 0.3v, r l =10k ?? to v dd /2, si and sck are tied low and cs is tied high. parameters sym min typ max units conditions amplifier input input offset voltage v os -275 ? +275 v g = +1, v dd = 4.0v input offset voltage drift ? v os / ? t a ?4 ?v/ct a = -40 to +85c power supply rejection ratio psrr 70 85 ? db g = +1 (note 1) input bias current i b ? 1 ? pa chx = v dd /2 input bias current over temperature i b ? ? 250 pa t a = -40 to +85c, chx = v dd /2 input impedance z in ?10 13 ||15 ? ? ||pf input voltage range v ivr v ss ? 0.3 ? v dd +0.3 v amplifier gain nominal gains ? ? 1 to 32 ? v/v +1, +2, +4, +5, +8, +10, +16 or +32 dc gain error g = +1 g e -0.1 ? +0.1 % v out ? 0.3v to v dd ?? 0.3v g ? +2 g e -1.0 ? +1.0 % v out ? 0.3v to v dd ?? 0.3v dc gain drift g = +1 ? g/ ? t a ? 0.0002 ? %/c t a = -40 to +85c g ? +2 ? g/ ? t a ? 0.0004 ? %/c t a = -40 to +85c internal resistance r lad 3.4 4.9 6.4 k ? (note 1) internal resistance over temperature ? r lad / ? t a ? +0.028 ? %/c (note 1) t a = -40 to +85c amplifier output dc output non-linearity g = +1 v onl ? 0.003 ? % of fsr v out = 0.3v to v dd ?? 0.3v, v dd = 5.0v g ? +2 v onl ? 0.001 ? % of fsr v out = 0.3v to v dd ?? 0.3v, v dd = 5.0v maximum output voltage swing v oh , v ol v ss +20 ? v dd -100 mv g ? +2; 0.5v output overdrive v ss +60 ? v dd -60 g ? +2; 0.5v output overdrive, v ref = v dd /2 short-circuit current i o(sc) ?30 ? ma note 1: r lad (r f + r g in figure 4-1) connects v ref , v out and the inverting input of the internal amplifier. the mcp6s22 has v ref tied internally to v ss , so v ss is coupled to the internal amplifier and the psrr spec describes psrr+ only. we recommend the mcp6s22?s v ss pin be tied directly to ground to avoid noise problems. 2: i q includes current in r lad (typically 60 a at v out = 0.3v). both i q and i q_shdn exclude digital switching currents. 3: the output goes hi-z and the registers reset to their defaults; see section 5.4, ?power-on reset?.
? 2003-2012 microchip technology inc. ds21117b-page 3 mcp6s21/2/6/8 power supply supply voltage v dd 2.5 ? 5.5 v quiescent current i q 0.5 1.0 1.35 ma i o = 0 (note 2) quiescent current, shutdown mode i q_shdn ?0.5 1.0 ai o = 0 (note 2) power-on reset por trip voltage v por 1.2 1.7 2.2 v (note 3) por trip voltage drift ? v por / ? t? -3.0 ? mv/ct a = -40c to+85c dc characteristics (continued) electrical specifications: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref = v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 to ch7 = 0.3v, r l =10k ?? to v dd /2, si and sck are tied low and cs is tied high. parameters sym min typ max units conditions note 1: r lad (r f + r g in figure 4-1) connects v ref , v out and the inverting input of the internal amplifier. the mcp6s22 has v ref tied internally to v ss , so v ss is coupled to the internal amplifier and the psrr spec describes psrr+ only. we recommend the mcp6s22?s v ss pin be tied directly to ground to avoid noise problems. 2: i q includes current in r lad (typically 60 a at v out = 0.3v). both i q and i q_shdn exclude digital switching currents. 3: the output goes hi-z and the registers reset to their defaults; see section 5.4, ?power-on reset?. ac characteristics electrical specifications: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref = v ss , g = +1 v/v, input = ch0 =(0.3v)/g, ch1 to ch7=0.3v, r l =10k ?? to v dd /2, c l = 60 pf, si and sck are tied low, and cs is tied high. parameters sym min typ max units conditions frequency response -3 db bandwidth bw ? 2 to 12 ? mhz all gains; v out < 100 mv p-p (note 1) gain peaking gpk ? 0 ? db all gains; v out < 100 mv p-p total harmonic distortion plus noise f = 1 khz, g = +1 v/v thd+n ? 0.0015 ? % v out = 1.5v 1.0v pk , v dd = 5.0v, bw = 22 khz f = 1 khz, g = +4 v/v thd+n ? 0.0058 ? % v out = 1.5v 1.0v pk , v dd = 5.0v, bw = 22 khz f = 1 khz, g = +16 v/v thd+n ? 0.023 ? % v out = 1.5v 1.0v pk , v dd = 5.0v, bw = 22 khz f = 20 khz, g = +1 v/v thd+n ? 0.0035 ? % v out = 1.5v 1.0v pk , v dd = 5.0v, bw = 80 khz f = 20 khz, g = +4 v/v thd+n ? 0.0093 ? % v out = 1.5v 1.0v pk , v dd = 5.0v, bw = 80 khz f = 20 khz, g = +16 v/v thd+n ? 0.036 ? % v out = 1.5v 1.0v pk , v dd = 5.0v, bw = 80 khz step response slew rate sr ? 4.0 ? v/s g = 1, 2 ? 11 ? v/s g = 4, 5, 8, 10 ? 22 ? v/s g = 16, 32 noise input noise voltage e ni ?3.2?v p-p f = 0.1 hz to 10 khz (note 2) ? 26 ? f = 0.1 hz to 200 khz (note 2) input noise voltage density e ni ?10?nv/ ? hz f = 10 khz (note 2) input noise current density i ni ?4?fa/ ? hz f = 10 khz note 1: see table 4-1 for a list of typical numbers. 2: e ni and e ni include ladder resistance noise. see figure 2-33 for e ni vs. g data.
mcp6s21/2/6/8 ds21117b-page 4 ? 2003-2012 microchip technology inc. digital characteristics electrical specifications: unless otherwise indicated, t a = +25c, v dd = +2.5v to +5.5v, v ss = gnd, v ref = v ss , g = +1 v/v, input = ch0 = (0.3v)/g, ch1 to ch7 = 0.3v, r l =10k ?? to v dd /2, c l = 60 pf, si and sck are tied low, and cs is tied high. parameters sym min typ max units conditions spi inputs (cs , si, sck) logic threshold, low v il 0 ? 0.3v dd v input leakage current i il -1.0 ? +1.0 a logic threshold, high v ih 0.7v dd ?v dd v amplifier output leakage current ? -1.0 ? +1.0 a in shutdown mode spi output (so, for mcp6s26 and mcp6s28) logic threshold, low v ol v ss ?v ss +0.4 v i ol = 2.1 ma, v dd = 5v logic threshold, high v oh v dd -0.5 ? v dd vi oh = -400 a spi timing pin capacitance c pin ? 10 ? pf all digital i/o pins input rise/fall times (cs , si, sck) t rfi ??2s note 1 output rise/fall times (so) t rfo ? 5 ? ns mcp6s26 and mcp6s28 cs high time t csh 40 ? ? ns sck edge to cs fall setup time t cs0 10 ? ? ns sck edge when cs is high cs fall to first sck edge setup time t cssc 40 ? ? ns sck frequency f sck ??10mhzv dd = 5v (note 2) sck high time t hi 40 ? ? ns sck low time t lo 40 ? ? ns sck last edge to cs rise setup time t sccs 30 ? ? ns cs rise to sck edge setup time t cs1 100 ? ? ns sck edge when cs is high si set-up time t su 40 ? ? ns si hold time t hd 10 ? ? ns sck to so valid propagation delay t do ? ? 80 ns mcp6s26 and mcp6s28 cs rise to so forced to zero t soz ? ? 80 ns mcp6s26 and mcp6s28 channel and gain select timing channel select time t ch ? 1.5 ? s chx = 0.6v, chy =0.3v, g = 1, chx to chy select c s = 0.7v dd to v out 90% point gain select time t g ? 1 ? s chx = 0.3v, g = 5 to g = 1 select, c s = 0.7v dd to v out 90% point shutdown mode timing out of shutdown mode (cs goes high) to amplifier output turn-on time t on ?3.510s cs = 0.7v dd to v out 90% point into shutdown mode (cs goes high) to amplifier output high-z turn-off time t off ?1.5?s cs = 0.7v dd to v out 90% point por timing power-on reset power-up time t rpu ?30?sv dd = v por - 0.1v to v por + 0.1v, 50% v dd to 90% v out point power-on reset power-down time t rpd ?10?sv dd = v por + 0.1v to v por - 0.1v, 50% v dd to 90% v out point note 1: not tested in production. set by design and characterization. 2: when using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of propagation delay time (t do ? 80 ns), data input setup time (t su ? 40 ns), sck high time (t hi ? 40 ns), and sck rise and fall times of 5 ns. maximum f sck is, therefore, ? 5.8 mhz.
? 2003-2012 microchip technology inc. ds21117b-page 5 mcp6s21/2/6/8 temperature characteristics figure 1-1: channel select timing diagram. figure 1-2: pga shutdown timing diagram (must enter correct commands before cs goes high). figure 1-3: gain select timing diagram. figure 1-4: por power-up and power- down timing diagram. electrical specifications: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +85 c operating temperature range t a -40 ? +125 c (note 1) storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 8l-pdip ? ja ?85?c/w thermal resistance, 8l-soic ? ja ?163?c/w thermal resistance, 8l-msop ? ja ?206?c/w thermal resistance, 14l-pdip ? ja ?70?c/w thermal resistance, 14l-soic ? ja ?120?c/w thermal resistance, 14l-tssop ? ja ?100?c/w thermal resistance, 16l-pdip ? ja ?70?c/w thermal resistance, 16l-soic ? ja ?90?c/w note 1: the mcp6s21/2/6/8 family of pgas operates over this extended temperature range, but with reduced performance. operation in this range must not cause t j to exceed the maximum junction temperature (150c). cs v out t ch 0.6v 0.3v cs t off v out t on hi-z hi-z i ss 500 na (typ) 1.0 ma (typ) 0.3v cs v out t g 1.5v 0.3v v dd t rpd v out t rpu hi-z hi-z v por - 0.1v v por - 0.1v v por + 0.1v 0.3v i ss 500 na (typ) 1.0 ma (typ)
mcp6s21/2/6/8 ds21117b-page 6 ? 2003-2012 microchip technology inc. figure 1-5: detailed spi serial interface timing, spi 0,0 mode. figure 1-6: detailed spi serial interface timing, spi 1,1 mode. cs sck si t su t hd t cssc t sccs t csh so (first 16 bits out are always zeros) t do t soz t lo t hi 1/f sck t cs0 t cs1 cs sck si t su t hd t cssc t sccs so (first 16 bits out are always zeros) t do t soz t hi t lo 1/f sck t cs1 t csh t cs0
? 2003-2012 microchip technology inc. ds21117b-page 7 mcp6s21/2/6/8 1.1 dc output voltage specs / model 1.1.1 ideal model the ideal pga output voltage (v out ) is: equation (see figure 1-7). this equation holds when there are no gain or offset errors and when the v ref pin is tied to a low impedance source (<< 0.1 ? ) at ground potential (v ss = 0v). 1.1.2 linear model the pga?s linear region of operation, including offset and gain errors, is modeled by the line v o_linear , shown in figure 1-7. equation the endpoints of this line are at v o_ideal =0.3v and v dd -0.3v. the gain and offset specifications referred to in the electrical specifications are related to figure 1-7, as follows: equation figure 1-7: output voltage model with the standard condition v ref = v ss = 0v. 1.1.3 output non-linearity figure 1-8 shows the integral non-linearity (inl) of the output voltage. equation the output non-linearity specification in the electrical specifications is related to figure 1-8 by: equation figure 1-8: output voltage inl with the standard condition v ref = v ss = 0v. v o_ideal gv in = v ref v ss 0v == where: g is the nominal gain v o_linear g1 g e + ?? v in 0.3v v os + ? ?? 0.3v + = v ref v ss 0v == g e 100% v 2 v 1 ? gv dd 0.6v ? ?? ------------------------------------- - = v os v 1 g1 g e + ?? ------------------------ - = gt a ? ? ? g e ? t a ? --------- - = g+1 = 0 0 0.3 v dd -0.3 v dd v o u t v out (v) v in (v) 0.3 v dd - 0.3 v dd g gg v 1 v o _ i d e a l v o _ l i n e a r v 2 inl v out v o_linear ? = v onl max v 4 v 3 ? ?? v dd 0.6v ? -------------------------------- - = 0 v 3 v 4 inl (v) v in (v) 0.3 v dd - 0.3 v dd g gg 0
mcp6s21/2/6/8 ds21117b-page 8 ? 2003-2012 microchip technology inc. 1.1.4 different v ref conditions some of the plots in section 2.0, ?typical performance curves?, have the conditions v ref =v dd /2 or v ref =v dd . the equations and figures above are eas- ily modified for these conditions. the ideal v out becomes: equation the complete linear model is: equation where the new v in endpoints are: equation the equations for extracting the specifications do not change. v o_ideal v ref gv in v ref ? ?? + = v dd v ref v ss ? 0v = ? v o_linear g1 g e + ?? v in v in_l v os + ? ?? 0.3v + = v in_l 0.3v v ref ? gv ref + ------------------------------ = v in_r v dd 0.3v ? v ref ? gv ref + ----------------------------------------------- =
? 2003-2012 microchip technology inc. ds21117b-page 9 mcp6s21/2/6/8 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = +5.0v, v ss =gnd, v ref =v ss , g= +1 v/v, input = ch0 = (0.3v)/g, ch1 to ch7 = 0.3v, r l =10k ?? to v dd /2, and c l = 60 pf. figure 2-1: dc gain error, g = +1. figure 2-2: dc gain error, g ? +2. figure 2-3: ladder resistance drift. figure 2-4: dc gain drift, g = +1. figure 2-5: dc gain drift, g ? +2. figure 2-6: input offset voltage, v dd = 4.0v. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% -0.040 -0.036 -0.032 -0.028 -0.024 -0.020 -0.016 -0.012 -0.008 -0.004 0.000 0.004 dc gain error (%) percentage of occurrences 420 samples g = +1 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 dc gain error (%) percentage of occurrences 420 samples g +2 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 0.023 0.024 0.025 0.026 0.027 0.028 0.029 0.030 0.031 ladder resistance drift (%/c) percentage of occurrences 420 samples t a = -40 to +125c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% -0.0006 -0.0005 -0.0004 -0.0003 -0.0002 -0.0001 0.0000 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 dc gain drift (%/c) percentage of occurrences 420 samples g = +1 t a = -40 to +125c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% 24% -0.0020 -0.0016 -0.0012 -0.0008 -0.0004 0.0000 0.0004 0.0008 0.0012 0.0016 0.0020 dc gain drift (%/c) percentage of occurrences 420 samples g +2 t a = -40 to +125c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% -240 -200 -160 -120 -80 -40 0 40 80 120 160 200 240 input offset voltage (v) percentage of occurrences 360 samples v dd = 4.0 v g = +1
mcp6s21/2/6/8 ds21117b-page 10 ? 2003-2012 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +5.0v, v ss =gnd, v ref =v ss , g= +1 v/v, input = ch0 = (0.3v)/g, ch1 to ch7 = 0.3v, r l =10k ?? to v dd /2, and c l = 60 pf. figure 2-7: input offset voltage vs. v ref voltage. figure 2-8: dc output non-linearity vs. supply voltage. figure 2-9: input noise voltage density vs. frequency. figure 2-10: input offset voltage drift. figure 2-11: dc output non-linearity vs. output swing. figure 2-12: input noise voltage density vs. gain. -200 -150 -100 -50 0 50 100 150 200 0.00.51.01.52.02.53.03.54.04.55.05.5 v ref voltage (v) input offset voltage (v) v dd = +5.5 v dd = +2.5 g = +1 0.00001 0.0001 0.001 0.01 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) dc output non-linearity, input referred (% of fsr) v onl /g, g = +1 v onl /g, g = +2 v onl /g, g +4 v out = 0.3v to v dd -0.3v 1 10 100 1000 0.1 1 10 100 1000 10000 100000 frequency (hz) input noise voltage density (nv/ hz) 1k 10k 100k 1 10 100 0.1 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 input offset voltage drift (v/c) percentage of occurrences 420 samples t a = -40 to +125c g = +1 0.0001% 0.0010% 0.0100% 110 output voltage swing (v p-p ) dc output non-linearity, input referred (%) v onl /g, g +2 v onl /g, g = +1 v dd = +5.5 v 0 1 2 3 4 5 6 7 8 9 10 11 12 12458101632 gain (v/v) input noise voltage density (nv/ hz) f = 10 khz
? 2003-2012 microchip technology inc. ds21117b-page 11 mcp6s21/2/6/8 note: unless otherwise indicated, t a =+25c, v dd = +5.0v, v ss = gnd, v ref =v ss , g= +1 v/v, input = ch0 = (0.3v)/g, ch1 to ch7 = 0.3v, r l =10k ?? to v dd /2, and c l = 60 pf. figure 2-13: psrr vs. ambient temperature. figure 2-14: input bias current vs. ambient temperature. figure 2-15: bandwidth vs. capacitive load. figure 2-16: psrr vs. frequency. figure 2-17: input bias current vs. input voltage. figure 2-18: gain peaking vs. capacitive load. 70 80 90 100 110 120 -50 -25 0 25 50 75 100 125 ambient temperature (c) power supply rejection ratio (db) 1 10 100 1,000 55 65 75 85 95 105 115 125 ambient temperature (c) input bias current (pa) ch0 = v dd v dd = 5.5 v 1 10 100 10 100 1000 capacitive load (pf) bandwidth (mhz) g = +1 g = +4 g = +16 40 50 60 70 80 90 100 1 0 100 10 00 1 0000 1000 00 frequency (hz) power supply rejection ratio (db) v dd = 2.5 v v dd = 5.5 v 1k 10k 100k 10 100 input referred 1 10 100 1,000 10,000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) input bias current (pa) t a = +85c v dd = 5.5 v t a = +125c 0 1 2 3 4 5 6 7 10 100 1000 capacitive load (pf) gain peaking (db) g = +1 g = +4 g = +16
mcp6s21/2/6/8 ds21117b-page 12 ? 2003-2012 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +5.0v, v ss = gnd, v ref =v ss , g= +1 v/v, input = ch0 = (0.3v)/g, ch1 to ch7 = 0.3v, r l =10k ?? to v dd /2, and c l = 60 pf. figure 2-19: gain vs. frequency. figure 2-20: histogram of quiescent current in shutdown mode. figure 2-21: output voltage headroom vs. output current. figure 2-22: quiescent current vs. supply voltage. figure 2-23: quiescent current in shutdown mode vs. ambient temperature. figure 2-24: output short circuit current vs. supply voltage. -20 -10 0 10 20 30 40 1.e+05 1.e+06 1.e+07 1.e+08 frequency (hz) gain (db) g = +2 g = +1 1m 10m 100m 100k g = +32 g = +16 g = +10 g = +8 g = +5 g = +4 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 quiescent current in shutdown (a) percentage of occurrences 420 samples v dd = 5.0 v 1 10 100 0.1 1 10 output current magnitude (ma) output voltage headroom (mv) v dd - v oh and v ol - v ss v dd = +5.5v v dd = +2.5v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) quiescent current (ma) t a = +125c t a = +85c t a = +25c t a = -40c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -25 0 25 50 75 100 125 ambient temperature (c) quiescent current in shutdown (a) in shutdown mode v dd = 5.0 v 0 5 10 15 20 25 30 35 40 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) output short circuit current (ma) t a = +125c t a = +85c t a = +25c t a = -40c
? 2003-2012 microchip technology inc. ds21117b-page 13 mcp6s21/2/6/8 note: unless otherwise indicated, t a =+25c, v dd = +5.0v, v ss = gnd, v ref =v ss , g= +1 v/v, input = ch0 = (0.3v)/g, ch1 to ch7 = 0.3v, r l =10k ?? to v dd /2, and c l = 60 pf. figure 2-25: thd plus noise vs. frequency, v out = 2 v p-p . figure 2-26: small signal pulse response. figure 2-27: channel select timing. figure 2-28: thd plus noise vs. frequency, v out = 4 v p-p . figure 2-29: large signal pulse response. figure 2-30: gain select timing. 0.001 0.01 0.1 1 1.e+02 1.e+03 1.e+0 4 1.e+05 frequency (hz) thd + noise (%) measurement bw = 80 khz v out = 2 v p-p v dd = 5.0 v 100 1k 100k 10k g = +4 g = +1 g = +16 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 0 .00 e+0 0 2.0 0e-0 7 4.00e-07 6.00e-07 8.00e-07 1.0 0e-0 6 1.2 0e-0 6 1.40e- 06 1.60e- 06 1.80 e-06 2 .00 e-06 time (200 ns/div) output voltage (10 mv/div) -250 -200 -150 -100 -50 0 50 100 150 200 250 normalized input voltage (50 mv/div) v dd = +5.0v v out , g = +1 g = +5 g = +32 gv in 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.0 0e+00 5.00e-07 1.00e-06 1.50e-06 2.00e-06 2.50e-06 3 .00 e-06 3 .5 0e-0 6 4.00 e-06 4 .5 0e-0 6 5.0 0e-0 6 time (500 ns/div) output voltage (v) -20 -15 -10 -5 0 5 10 15 20 chip select voltage (v) 5 0 v out (ch0 = 0.6v, g = +1) v out (ch1 = 0.3v, g = +1) cs cs 0.001 0.01 0.1 1 1.e+02 1.e+0 3 1.e+04 1.e+05 frequency (hz) thd + noise (%) measurement bw = 80 khz v out = 4 v p-p v dd = 5.0 v 100 1k 100k 10k g = +4 g = +1 g = +16 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.00e+00 5 .00 e-07 1.0 0e-0 6 1.5 0e-0 6 2.00e- 06 2.50e-06 3.00 e-06 3.5 0e-0 6 4 .0 0e-0 6 4.50e- 06 5.00e-06 time (500 ns/div) output voltage (v) -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 normalized input voltage (1v/div) v dd = +5.0v gv in v out , g = +1 g = +5 g = +32 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.00 e+0 0 5.00e- 07 1.00e- 06 1.50e-06 2.00e-06 2.5 0e-0 6 3.00e- 06 3.50e-06 4.00e-06 4.50 e-06 5.0 0e-0 6 time (500 ns/div) output voltage (v) -20 -15 -10 -5 0 5 10 15 20 chip select voltage (v) 5 0 v out (ch0 = 0.3v, g = +5) v out (ch0 = 0.3v, g = +1) cs cs
mcp6s21/2/6/8 ds21117b-page 14 ? 2003-2012 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +5.0v, v ss = gnd, v ref =v ss , g= +1 v/v, input = ch0 = (0.3v)/g, ch1 to ch7 = 0.3v, r l =10k ?? to v dd /2, and c l = 60 pf. figure 2-31: output voltage vs. shutdown mode. figure 2-32: por trip voltage. figure 2-33: output voltage swing vs. frequency. figure 2-34: the mcp6s21/2/6/8 family shows no phase reversal under overdrive. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0e+00 1.0e-06 2 .0 e-06 3.0 e-06 4.0e-0 6 5.0e-06 6 .0e-06 7.0 e-06 8.0e-0 6 9.0e- 06 1.0e-05 time (1 s/div) output voltage (mv) -25 -20 -15 -10 -5 0 5 10 15 20 25 chip select voltage (v) 5 0 v out is "on" (ch0 = 0.3v, g = +1) shutdown cs cs shutdown 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 1.60 1.64 1.68 1.72 1.76 1.80 1.84 1.88 por trip voltage (v) percentage of occurrences 420 samples 0.1 1 10 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) output voltage swing (v p-p ) v dd = 2.5 v v dd = 5.5 v g = +1, +2 g = +4 to +10 g = +16, +32 10k 100k 10m 1m -1 0 1 2 3 4 5 6 0.0e+00 1.0e-0 3 2.0e- 03 3 .0e-03 4.0e-0 3 5.0e-03 6 .0e-03 7.0e-0 3 8.0e-03 9 .0e-03 1.0e-0 2 time (1 ms/div) input, output voltage (v) v dd = 5.0 v g = +1 v/v v in v out
? 2003-2012 microchip technology inc. ds21117b-page 15 mcp6s21/2/6/8 3.0 pin descriptions the descriptions of the pins are listed in table 3-1. table 3-1: pin function table 3.1 analog output the output pin (v out ) is a low-impedance voltage source. the selected gain (g), selected input (ch0- ch7) and voltage at v ref determine its value. 3.2 analog inputs (ch0 thru ch7) the inputs ch0 through ch7 connect to the signal sources. they are high-impedance cmos inputs with low bias currents. the internal mux selects which one is amplified to the output. 3.3 external reference voltage (v ref ) the v ref pin should be at a voltage between v ss and v dd (the mcp6s22 has v ref tied internally to v ss ). the voltage at this pin shifts the output voltage. 3.4 power supply (v ss and v dd ) the positive power supply pin (v dd ) is 2.5v to 5.5v higher than the negative power supply pin (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need a local bypass capacitor (0.1 f) at the v dd pin. it can share a bulk capacitor with nearby analog parts (typically 2.2 f to 10 f within 4 inches (100 mm) of the v dd pin. 3.5 digital inputs the spi interface inputs are: chip select (cs ), serial input (si) and serial clock (sck). these are schmitt- triggered, cmos logic inputs. 3.6 digital output the mcp6s26 and mcp6s28 devices have a spi interface serial output (so) pin. this is a cmos push- pull output and does not ever go high-z. once the device is deselected (cs goes high), so is forced low. this feature supports daisy chaining, as explained in section 5.3, ?daisy chain configuration?. mcp6s21 mcp6s22 mcp6s26 mcp6s28 symbol description 1111v out analog output 2222ch0analog input ? 3 3 3 ch1 analog input ? ? 4 4 ch2 analog input ? ? 5 5 ch3 analog input ? ? 6 6 ch4 analog input ? ? 7 7 ch5 analog input ? ? ? 8 ch6 analog input ? ? ? 9 ch7 analog input 3?810v ref external reference pin 44911v ss negative power supply 5 5 10 12 cs spi chip select 6 6 11 13 si spi serial data input ? ? 12 14 so spi serial data output 7 7 13 15 sck spi clock input 8 8 14 16 v dd positive power supply
mcp6s21/2/6/8 ds21117b-page 16 ? 2003-2012 microchip technology inc. 4.0 analog functions the mcp6s21/2/6/8 family of programmable gain amplifiers (pga) are based on simple analog building blocks (see figure 4-1). each of these blocks will be explained in more detail in the following sub-sections. figure 4-1: pga block diagram. 4.1 input mux the mcp6s21 has one input, the mcp6s22 and mcp6s25 have two inputs, the mcp6s26 has six inputs and the mcp6s28 has eight inputs (see figure 4-1). for the lowest input current, float unused inputs. tying these pins to a voltage near the used channels also works well. for simplicity, they can be tied to v ss or v dd , but the input current may increase. the one channel mcp6s21 has the lowest input bias current, while the eight channel mcp6s28 has the highest. there is about a 2:1 ratio in i b between these parts. 4.2 internal op amp the internal op amp provides the right combination of bandwidth, accuracy and flexibility. 4.2.1 compensation capacitors the internal op amp has three compensation capaci- tors connected to a switching network. they are selected to give good small signal bandwidth at high gains, and good slew rate (full power bandwidth) at low gains. the change in bandwidth as gain changes is between 2 mhz and 12 mhz. refer to table 4-1 for more information. table 4-1: gain vs. internal compensation capacitor mcp6s21 ?one input (ch0), no so pin mcp6s22 ?two inputs (ch0, ch1), v ref tied internally to v ss , no so pin mcp6s26 ?six inputs (ch0 to ch5) mcp6s28 ?eight inputs (ch0 to ch7) v out v ref v dd cs si so sck ch1 ch0 ch3 ch2 ch5 ch4 ch7 ch6 v ss 8 r f r g mux spi? logic por gain switches + - resistor ladder (r lad ) gain (v/v) internal compensation capacitor typical gbwp (mhz) typical sr (v/s) typical fpbw (mhz) typical bw (mhz) 1 large 12 4.0 0.30 12 2 large 12 4.0 0.30 6 4medium 20 11 0.70 10 5medium 20 11 0.70 7 8 medium 20 11 0.70 2.4 10 medium 20 11 0.70 2.0 16 small 64 22 1.6 5 32 small 64 22 1.6 2.0 note 1: fpbw is the full power bandwidth. these numbers are based on v dd = 5.0v. 2: no changes in dc performance (e.g., v os ) accompany a change in compensation capacitor. 3: bw is the closed-loop, small signal -3 db bandwidth.
? 2003-2012 microchip technology inc. ds21117b-page 17 mcp6s21/2/6/8 4.2.2 rail-to-rail input the input stage of the internal op amp uses two differ- ential input stages in parallel; one operates at low v in (input voltage), while the other operates at high v in . with this topology, the internal inputs can operate to 0.3v past either supply rail. the input offset voltage is measured at both v in =v ss - 0.3v and v dd + 0.3v to ensure proper operation. the transition between the two input stages occurs when v in ? v dd - 1.5v. for the best distortion and gain linearity, avoid this region of operation. 4.2.3 rail-to-rail output the maximum output voltage swing is the maximum swing possible under a particular output load. accord- ing to the specification table, the output can reach within 60 mv of either supply rail when r l =10k ?? and v ref = v dd /2. see figure 2-21 for typical performance under other conditions. 4.2.4 input voltage and phase reversal the amplifier family is designed with cmos input devices. it is designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-34 shows an input voltage exceeding both supplies with no resulting phase inversion. the maximum voltage that can be applied to the input pins (chx) is v ss - 0.3v to v dd + 0.3v. voltages on the inputs that exceed this absolute maximum rating can cause excessive current to flow in or out of the input pins. current beyond 2 ma can cause possible reli- ability problems. applications that exceed this rating must be externally limited with an input resistor, as shown in figure 4-2. figure 4-2: r in limits the current flow into an input pin. 4.3 resistor ladder the resistor ladder shown in figure 4-1 (r lad = r f + r g ) sets the gain. placing the gain switches in series with the inverting input reduces the parasitic capaci- tance, distortion and gain mismatch. r lad is an additional load on the output of the pga and causes additional current draw from the supplies. in shutdown mode, r lad is still attached to the out and v ref pins. thus, these pins and the internal ampli- fier?s inverting input are all connected through r lad and the output is not high-z (unlike the external op amp). while r lad contributes to the output noise, its effect is small. refer to figure 2-12. 4.4 shutdown mode these pgas use a software shutdown command. when the spi interface sends a shutdown command, the internal op amp is shut down and its output placed in a high-z state. the resistive ladder is always connected between v ref and v out ; even in shutdown. this means that the output resistance will be on the order of 5 k ? and there will be a path for output signals to appear at the input. the power-on reset (por) circuitry will temporarily place the part in shutdown when activated. see section 5.4, ?power-on reset?, for details. r in v ss minimum expected v in ?? ? 2 ma --------------------------------------------------------------------------- - ? r in maximum expected v in ?? v dd ? 2 ma ------------------------------------------------------------------------------ - ? v in r in v out mcp6s2x chx
mcp6s21/2/6/8 ds21117b-page 18 ? 2003-2012 microchip technology inc. 5.0 digital functions the mcp6s21/2/6/8 pgas use a standard spi com- patible serial interface to receive instructions from a controller. this interface is configured to allow daisy chaining with other spi devices. there is an internal por (power on reset) that resets the registers under low power conditions. 5.1 spi timing chip select (cs ) toggles low to initiate communication with these devices. the first byte of each si word (two bytes long) is the instruction byte, which goes into the instruction register. the instruction register points the second byte to its destination. in a typical application, cs is raised after one word (16 bits) to implement the desired changes. section 5.3, ?registers?, covers applications using multiple 16-bit words. so goes low after cs goes high; it has a push-pull output that does not go into a high-z state. the mcp6s21/2/6/8 devices operate in spi modes 0,0 and 1,1. in 0,0 mode, the clock idles in the low state (figure 5-1) and, in 1,1 mode, the clock idles in the high state (figure 5-2). in both modes, si data is loaded into the pga on the rising edge of sck and so data is clocked out on the falling edge of sck. in 0,0 mode, the falling edge of cs also acts as the first falling edge of sck (see figure 5-1). there must be multiples of 16 clocks (sck) while cs is low or commands will abort (see section 5.3, ?registers?). figure 5-1: serial bus sequence for the pga; spi 0,0 mode (see figure 1-5). figure 5-2: serial bus sequence for the pga; spi 1,1 mode (see figure 1-6). 123456789 10 11 12 13 14 15 16 bit 7 cs sck si instruction byte data byte bit 0 bit 7 bit 0 so (first 16 bits out are always zeros) 12345678910111213141516 bit 7 cs sck si instruction byte data byte bit 0 bit 7 bit 0 so (first 16 bits out are always zeros)
? 2003-2012 microchip technology inc. ds21117b-page 19 mcp6s21/2/6/8 5.2 registers the analog functions are programmed through the spi interface using 16-bit words (see figure 5-1 and figure 5-2). this data is sent to two of three 8-bit regis- ters: instruction register (register 5-1), gain register (register 5-2) and channel register (register 5-3). the power-up defaults for these three registers are: ? instruction register: 000x xxx0 ? gain register: xxxx x000 ? channel register: xxxx x000 thus, these devices are initially programmed with the instruction register set for nop (no operation), a gain of +1 v/v and ch0 as the input channel. 5.2.1 instruction register the instruction register has 3 command bits and 1 indirect address bit; see register 5-1. the command bits include a nop ( 000 ) to support daisy chaining (see section 5.3, ?registers?); the other nop commands shown should not be used (they are reserved for future use). the device is brought out of shutdown mode when a valid command, other than nop or shutdown, is sent and cs is raised. register 5-1: instruction register w-0 w-0 w-0 u-x u-x u-x u-x w-0 m2 m1 m0 ? ? ? ?a0 bit 7 bit 0 bit 7-5 m2-m0: command bits 000 = nop (default) (note 1) 001 = pga enters shutdown mode as soon as a full 16-bit word is sent and cs is raised. (notes 1 and 2) 010 = write to register. 011 = nop (reserved for future use) (note 1) 1xx = nop (reserved for future use) (note 1) bit 4-1 unimplemented: read as ?0? (reserved for future use) bit 0 a0: indirect address bit 1 = addresses the channel register 0 = addresses the gain register (default) note 1: all other bits in the 16-bit word (including a0) are ?don?t cares?. 2: the device exits shutdown mode when a valid command (other than nop or shut- down) is sent and cs is raised; that valid command will be executed. shutdown does not toggle. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
mcp6s21/2/6/8 ds21117b-page 20 ? 2003-2012 microchip technology inc. 5.2.2 setting the gain the amplifier can be programmed to produce binary and decimal gain settings between +1 v/v and +32 v/v. register 5-2 shows the details. at the same time, differ- ent compensation capacitors are selected to optimize the bandwidth vs. slew rate trade-off (see table 4-1). register 5-2: gain register u-x u-x u-x u-x u-x w-0 w-0 w-0 ? ? ? ? ? g2g1g0 bit 7 bit 0 bit 7-3 unimplemented: read as ?0? (reserved for future use) bit 2-0 g2-g0: gain select bits 000 = gain of +1 (default) 001 = gain of +2 010 = gain of +4 011 = gain of +5 100 = gain of +8 101 = gain of +10 110 = gain of +16 111 = gain of +32 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003-2012 microchip technology inc. ds21117b-page 21 mcp6s21/2/6/8 5.2.3 changing the channel if the instruction register is programmed to address the channel register, the multiplexed inputs of the mcp6s22, mcp6s26 and mcp6s28 can be changed per register 5-3. register 5-3: channel register u-x u-x u-x u-x u-x w-0 w-0 w-0 ? ? ? ? ? c2c1c0 bit 7 bit 0 bit 7-3 unimplemented: read as ?0? (reserved for future use) bit 2-0 c2-c0: channel select bits mcp6s21 000 = ch0 (default) 001 = ch0 001 = ch0 011 = ch0 100 = ch0 101 = ch0 110 = ch0 111 = ch0 mcp6s22 ch0 (default) ch1 ch0 ch1 ch0 ch1 ch0 ch1 mcp6s26 ch0 (default) ch1 ch2 ch3 ch4 ch5 ch0 ch0 mcp6s28 ch0 (default) ch1 ch2 ch3 ch4 ch5 ch6 ch7 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
mcp6s21/2/6/8 ds21117b-page 22 ? 2003-2012 microchip technology inc. 5.2.4 shutdown command the software shutdown command allows the user to put the amplifier into a low power mode (see register 5-1). in this shutdown mode, most pins are high impedance (section 4.4, ?shutdown mode?, and section 5.1, ?spi timing?, cover the exceptions at pins v ref, v out and so). once the pga has entered shutdown mode, it will remain in this mode until either a valid command is sent to the device (other than nop or shutdown), or the device is powered down and back up again. the internal registers maintain their values while in shutdown. once brought out of shutdown mode, the part comes back to its previous state (see section 5.4 for excep- tions to this rule). this makes it possible to bring the device out of shutdown mode using one command; send a command to select the current channel (or gain) and the device will exit shutdown with the same state that existed before shutdown. 5.3 daisy chain configuration multiple devices can be connected in a daisy chain configuration by connecting the so pin from one device to the si pin on the next device and using common sck and cs lines (figure 5-3). this approach reduces pcb layout complexity. the example in figure 5-3 shows a daisy chain config- uration with two devices, although any number of devices can be configured this way. the mcp6s21 and mcp6s22 can only be used at the far end of the daisy chain because they do not have a serial data out (so) pin. as shown in figure 5-4 and figure 5-5, both si and so data are sent in 16-bit (2 byte) words. these devices abort any command that is not a multiple of 16 bits. when using the daisy chain configuration, the maxi- mum clock speed possible is reduced to ? 5.8 mhz because of the so pin?s propagation delay (see electrical specifications). the internal spi shift register is automatically loaded with zeros whenever cs goes high (a command is exe- cuted). thus, the first 16-bits out of the so pin once c s line goes low are always zeros. this means that the first command loaded into the next device in the daisy chain is a nop . this feature makes it possible to send shorter command and data byte strings when the far- thest devices do not need to change. for example, if there were three devices on the chain and only the mid- dle device needed changing, only 32 bytes of data need to be transmitted (for the first and middle devices), and the last device on the chain would receive a nop when the cs pin is raised to execute the command. figure 5-3: daisy chain configuration. microcontroller so cs sck si cs sck so device 1 device 1 00100000 00000000 so cs sck si device 2 device 2 00000000 00000000 1. set cs low. 2. clock out the instruction and data for device 2 (16 clocks) to device 1. 3. device 1 automatically clocks out all zeros (first 16 clocks) to device 2. 4. clock out the instruction and data for device 1 (16 clocks) to device 1. 5. device 1 automatically shifts data from device 1 to device 2 (16 clocks). 6. raise cs . device 1 01000001 00000111 device 2 00100000 00000000 pic ?
? 2003-2012 microchip technology inc. ds21117b-page 23 mcp6s21/2/6/8 figure 5-4: serial bus sequence for daisy-chain configuration; spi 0,0 mode. figure 5-5: serial bus sequence for daisy-chain configuration; spi 1,1 mode. 1 2 3 4 5 6 7 8 9 10111213141516 bit 7 cs sck si instruction byte data byte bit 0 bit 7 bit 0 so (first 16 bits out are always zeros) 1234567891011121314 1516 bit 7 instruction byte data byte bit 0 bit 7 bit 0 for device 2 for device 2 for device 1 for device 1 bit 7 instruction byte data byte bit 0 bit 7 bit 0 for device 2 for device 2 1 2 3 4 5 6 7 8 9 10111213141516 bit 7 cs sck si instruction byte data byte bit 0 bit 7 bit 0 so (first 16 bits out are always zeros) 1234567891011 1213141516 bit 7 instruction byte data byte bit 0 bit 7 bit 0 for device 2 for device 2 for device 1 for device 1 bit 7 instruction byte data byte bit 0 bit 7 bit 0 for device 2 for device 2
mcp6s21/2/6/8 ds21117b-page 24 ? 2003-2012 microchip technology inc. 5.4 power-on reset if the power supply voltage goes below the por trip voltage (v dd < v por ? 1.7v), the internal por circuit will reset all of the internal registers to their power-up defaults (this is a protection against low power supply voltages). the por circuit also holds the part in shut- down mode while it is activated. it temporarily overrides the software shutdown status. the por releases the shutdown circuitry once it is released (v dd > v por ). a 0.1 f bypass capacitor mounted as close as possi- ble to the v dd pin provides additional transient immunity.
? 2003-2012 microchip technology inc. ds21117b-page 25 mcp6s21/2/6/8 6.0 applications information 6.1 changing external reference voltage figure 6-1 shows a mcp6s21 with the v ref pin at 2.5v and v dd = 5.0v. this allows the pga to amplify signals centered on 2.5v, instead of ground-referenced signals. the voltage reference mcp1525 is buffered by a mcp6021, which gives a low output impedance ref- erence voltage from dc to high frequencies. the source driving the v ref pin should have an output impedance of ? 0.1 ? to maintain reasonable gain accuracy. figure 6-1: pga with different external reference voltage. 6.2 capacitive load and stability large capacitive loads can cause both stability prob- lems and reduced bandwidth for the mcp6s21/2/6/8 family of pgas (figure 2-17 and figure 2-18). this happens because a large load capacitance decreases the internal amplifier?s phase margin and bandwidth. if the pga drives a large capacitive load, the circuit in figure 6-2 can be used. a small series resistor (r iso ) at the v out improves the phase margin by making the load resistive at high frequencies. it will not, however, improve the bandwidth. figure 6-2: pga circuit for large capacitive loads. for c l ? 100 pf, a good estimate for r iso is 50 ? . this value can be fine-tuned on the bench. adjust r iso so that the step response overshoot and frequency response peaking are acceptable at all gains. 6.3 layout considerations good pc board layout techniques will help achieve the performance shown in the electrical characteristics and typical performance curves. it will also help minimize emc (electro-magnetic compatibility) issues. 6.3.1 component placement separate circuit functions; digital from analog, low speed from high speed, and low power from high power, as this will reduce crosstalk. keep sensitive traces short and straight, separating them from interfering components and traces. this is especially important for high frequency (low rise time) signals. use a 0.1 f supply bypass capacitor within 0.1 inch (2.5 mm) of the v dd pin. it must connect directly to the ground plane. a multi-layer ceramic chip capacitor, or high-frequency equivalent, works best. 6.3.2 signal coupling the input pins of the mcp6s21/2/6/8 family of opera- tional amplifiers (op amps) are high-impedance. this makes them especially susceptible to capacitively-cou- pled noise. using a ground plane helps reduce this problem. when noise is capacitively-coupled, the ground plane provides additional shunt capacitance to ground. when noise is magnetically coupled, the ground plane reduces the mutual inductance between traces. increasing the separation between traces makes a significant difference. changing the direction of one of the traces can also reduce magnetic coupling. it may help to locate guard traces next to the victim trace. they should be on both sides of the victim trace and be as close as possible. connect the guard traces to the ground plane at both ends, and in the middle, of long traces. 6.3.3 high frequency issues because the mcp6s21/2/6/8 pgas reach unity gain near 64 mhz when g = 16 and 32, it is important to use good pcb layout techniques. any parasitic coupling at high frequency might cause undesired peaking. filter- ing high frequency signals (i.e., fast edge rates) can help. to minimize high frequency problems: ? use complete ground and power planes ? use hf, surface mount components ? provide clean supply voltages and bypassing ? keep traces short and straight ? try a linear power supply (e.g., an ldo) v dd v ref mcp6s21 mcp1525 mcp6021 2.5v ref v dd v dd v in v out 1f v in mcp6s2x r iso v out c l
mcp6s21/2/6/8 ds21117b-page 26 ? 2003-2012 microchip technology inc. 6.4 typical applications 6.4.1 gain ranging figure 6-3 shows a circuit that measures the current i x . it benefits from changing the gain on the pga. just as a hand-held multimeter uses different measurement ranges to obtain the best results, this circuit makes it easy to set a high gain for small signals and a low gain for large signals. as a result, the required dynamic range at the pga?s output is less than at its input (by up to 30 db). figure 6-3: wide dynamic range current measurement circuit. 6.4.2 shifted gain range pga figure 6-4 shows a circuit using an mcp6021 at a gain of +10 in front of an mcp6s21. this changes the over- all gain range to +10 v/v to +320 v/v (from +1 v/v to +32 v/v). figure 6-4: pga with modified gain range. it is also easy to shift the gain range to lower gains (see figure 6-6). the mcp6021 acts as a unity gain buffer, and the resistive voltage divider shifts the gain range down to +0.1 v/v to +3.2 v/v (from +1 v/v to +32 v/v). figure 6-5: pga with lower gain range. 6.4.3 extended gain range pga figure 6-6 gives a +1 v/v to +1024 v/v gain range, which is much greater than the range for a single pga (+1 v/v to +32 v/v). the first pga provides input mul- tiplexing capability, while the second pga only needs one input. these devices can be daisy chained (section 5.3, ?daisy chain configuration?). figure 6-6: pga with extended gain range. 6.4.4 multiple sensor amplifier the multiple channel pgas (except the mcp6s21) allow the user to select which sensor appears on the output (see figure 6-7). these devices can also change the gain to optimize performance for each sensor. figure 6-7: pga with multiple sensor inputs. mcp6s2x v out i x r s v in mcp6021 mcp6s21 v out 10.0 k ? 1.11 k ? ? ? v in mcp6021 mcp6s21 v out 10.0 k ? 1.11 k ? ? ? v in v out mcp6s28 mcp6s21 sensor # 0 sensor # 1 sensor # 5 mcp6s26 v out
? 2003-2012 microchip technology inc. ds21117b-page 27 mcp6s21/2/6/8 6.4.5 expanded input pga figure 6-8 shows cascaded mcp6s28s that provide up to 15 input channels. obviously, sensors #7-14 have a high total gain range available, as explained in section 6.4.3, ?extended gain range?. these devices can be daisy chained (section 5.3, ?daisy chain configuration?). figure 6-8: pga with expanded inputs. 6.4.6 pic mcu with expanded input capability figure 6-9 shows an mcp6s28 driving an analog input to a pic microcontroller. this greatly expands the input capacity of the microcontroller, while adding the ability to select the appropriate gain for each source. figure 6-9: expanded input for a pic ? microcontroller. 6.4.7 adc driver the family of pga?s is well suited for driving analog-to- digital converters (adc). the binary gains (1, 2, 4, 8, 16 and 32) effectively add five more bits to the input range (see figure 6-10). this works well for applica- tions needing relative accuracy more than absolute accuracy (e.g., power monitoring). figure 6-10: pga as an adc driver. at low gains, the adc?s signal-to-noise ratio (snr) will dominate since the pgas input noise voltage den- sity is so low (10 nv/ ? hz @ 10 khz, typ.). at high gains, the pga?s noise will dominate the snr, but its low noise supports most applications. again, these pgas add the flexibility of selecting the best gain for an application. the low pass filter in the block diagram reduces the integrated noise at the mcp6s28?s output and serves as an anti-aliasing filter. this filter may be designed using microchip?s filterlab ? software, available at www.microchip.com. sensors sensors mcp6s28 mcp6s28 v out # 0-6 # 7-14 v in mcp6s28 pic ? microcontroller spi? v in out mcp6s28 lowpass filter 12 mcp3201
mcp6s21/2/6/8 ds21117b-page 28 ? 2003-2012 microchip technology inc. 7.0 packaging information 7.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) ( mcp6s21 , mcp6s22 ) example: 8-lead soic (150 mil) ( mcp6s21 , mcp6s22 ) example: xxxxxxxx xxxxyyww nnn mcp6s21 i/p256 0345 mcp6s21 i/sn0345 256 8-lead msop ( mcp6s21, mcp6s22 ) example: xxxxx ywwnnn mcp6s21i 345256 legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard marking consists of microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). for marking beyond this, certain price adders apply. please check with your microchip sales office.
? 2003-2012 microchip technology inc. ds21117b-page 29 mcp6s21/2/6/8 package marking information (con?t) 14-lead pdip (300 mil) ( mcp6s26 )example: 14-lead soic (150 mil) ( mcp6s26 ) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn xxxxxxxxxxx yywwnnn mcp6s26 -i/p xxxxxxxxxxxxxx 0345256 xxxxxxxxxxx mcp6s26 isl 0345256 xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx nnn yyww 14-lead tssop (4.4mm) ( mcp6s26 ) example: mcp6s26 ist 256 0345
mcp6s21/2/6/8 ds21117b-page 30 ? 2003-2012 microchip technology inc. package marking information (con?t) 16-lead pdip (300 mil) ( mcp6s28 )example: 16-lead soic (150 mil) ( mcp6s28 ) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxx yywwnnn mcp6s28 -i/p xxxxxxxxxxxxxx 0345256 xxxxxxxxxxxxx mcp6s28 -i/sl 0345256 xxxxxxxxxxxxxxxxxxxxxxxx
? 2003-2012 microchip technology inc. ds21117b-page 31 mcp6s21/2/6/8 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p ? e eb ? c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045.058.0701.141.461.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top ? 5 10 15 5 10 15 mold draft angle bottom ? 5 10 15 5 10 15 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6s21/2/6/8 ds21117b-page 32 ? 2003-2012 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle ? 048048 15 12 0 15 12 0 ? mold draft angle bottom 15 12 0 15 12 0 ? mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l ? c 45 ? ? a2 ? a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2003-2012 microchip technology inc. ds21117b-page 33 mcp6s21/2/6/8 8-lead plastic micro small outline package (ms) (msop) p a a1 a2 d l c dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not .037 .035 f footprint (reference) exceed .010" (0.254mm) per side. notes: drawing no. c04-111 *controlling parameter mold draft angle top mold draft angle bottom foot angle lead width lead thickness ? ? c b ? 7 7 .004 .010 0 .006 .012 (f) ? dimension limits overall height molded package thickness molded package width overall length foot length standoff overall width number of pins pitch a l e1 d a1 e a2 .016 .114 .114 .022 .118 .118 .002 .030 .193 .034 min p n units .026 nom 8 inches 1.00 0.95 0.90 .039 0.15 0.30 .008 .016 6 0.10 0.25 0 7 7 0.20 0.40 6 millimeters* 0.65 0.86 3.00 3.00 0.55 4.90 .044 .122 .028 .122 .038 .006 0.40 2.90 2.90 0.05 0.76 min max nom 1.18 0.70 3.10 3.10 0.15 0.97 max 8 ? e1 e b n 1 2 ? significant characteristic .184 .200 4.67 .5.08 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6s21/2/6/8 ds21117b-page 34 ? 2003-2012 microchip technology inc. 14-lead plastic dual in-line (p) ? 300 mil (pdip) e1 n d 1 2 eb ? e c a a1 b b1 l a2 p ? units inches* millimeters dimension limits min nom max min nom max number of pins n 14 14 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .740 .750 .760 18.80 19.05 19.30 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045.058.0701.141.461.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top ? 5 10 15 5 10 15 ? 5 10 15 5 10 15 mold draft angle bottom * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-005 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2003-2012 microchip technology inc. ds21117b-page 35 mcp6s21/2/6/8 14-lead plastic small outline (sl) ? narrow, 150 mil (soic) foot angle ? 048048 15 12 0 15 12 0 ? mold draft angle bottom 15 12 0 15 12 0 ? mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 8.81 8.69 8.56 .347 .342 .337 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 5.99 5.79 .244 .236 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 h l c ? 45 ? ? ? a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-065 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6s21/2/6/8 ds21117b-page 36 ? 2003-2012 microchip technology inc. 14-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 8 4 0 8 4 0 ? foot angle 10 5 0 10 5 0 ? mold draft angle bottom 10 5 0 10 5 0 ? mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b1 lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters* inches units l ? c ? 2 1 d n b p e1 e ? a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-087 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2003-2012 microchip technology inc. ds21117b-page 37 mcp6s21/2/6/8 16-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 .036 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 19.30 19.05 18.80 .760 .750 .740 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 16 16 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c ? eb e ? p l a2 b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-017 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6s21/2/6/8 ds21117b-page 38 ? 2003-2012 microchip technology inc. 16-lead plastic small outline (sl) ? narrow 150 mil (soic) foot angle ? 048048 15 12 0 15 12 0 ? mold draft angle bottom 15 12 0 15 12 0 ? mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 10.01 9.91 9.80 .394 .390 .386 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.44 1.32 .061 .057 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 16 16 n number of pins max nom min max nom min dimension limits millimeters inches* units ? a2 e1 1 2 l h n b 45 ? e p d ? ? c a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-108 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2003-2012 microchip technology inc. ds21117b-page 39 mcp6s21/2/6/8 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support data sheets products supported by a preliminary data sheet may have an e rrata sheet describing minor operational differences and recom- mended workarounds. to determine if an erra ta sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. -x /xx package temperature range device device: mcp6s21: one channel pga mcp6s21t: one channel pga (tape and reel for soic and msop) mcp6s22: two channel pga mcp6s22t: two channel pga (tape and reel for soic and msop) mcp6s26: six channel pga mcp6s26t: six channel pga (tape and reel for soic and tssop) mcp6s28: eight channel pga mcp6s28t: eight channel pga (tape and reel for soic) temperature range: i = -40c to +85c package: ms = plastic micro small outline (msop), 8-lead p = plastic dip (300 mil body), 8, 14, and 16-lead sn = plastic soic, (150 mil body), 8-lead sl = plastic soic (150 mil body), 14, 16-lead st = plastic tssop (4.4mm body), 14-lead examples: a) mcp6s21-i/p: one channel pga, pdip package. b) mcp6s21-i/sn: one channel pga, soic package. c) mcp6s21-i/ms: one channel pga, msop package. d) mcp6s22-i/ms: two channel pga, msop package. e) mcp6s22t-i/ms: tape and reel, two channel pga, msop package. f) mcp6s26-i/p: six channel pga, pdip package. g) mcp6s26-i/sn: six channel pga, soic package. h) mcp6s26t-i/st: tape and reel, six channel pga, tssop package. i) mcp6s28t-i/sl: tape and reel, eight channel pga, soic package.
mcp6s21/2/6/8 ds21117b-page 40 ? 2003-2012 microchip technology inc. notes:
? 2003-2012 microchip technology inc. ds21117b-page 41 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2003-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620767504 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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